Wishbone bus Architecture - A Survey and Comparison

Design and Verification Point-to-Point Architecture of WISHBONE Bus for System-on-Chip

SOC design is an integration of multi million transistors in a single chip for time to market and reducing the cost of the design. This paper presents point-to-point Architecture of WISHBONE bus. Main aim of the WISHBONE bus Architectures are to transfer the data from master to slave in different application without redesign of IP core. And that one will increase the productivity with reduction...

WISHBONE System-On-Chip (SoC) Interconnection Architecture for Portable IP Cores

Design and Implementation of Wishbone Bus Interface Architecture for SoC Integration USING VHDL ON FPGA

Wishbone bus is used to communicate variety of devices. While designing SOC, elastic interfacing between varieties of devices is crucial to get extreme performance. Wishbone bus used to interface a variety of devices due to its open structural design and many a free IP core with a Wishbone interface supplied by Open Cores association. Previously, IP cores used non-standard interconnection schem...

Open Cores for Digital Signal Processing

This paper presents the design and implementation of three System on Chip (SoC) cores, which implement the Digital Signal Processing (DSP) functions: Finite Impulse Response (FIR) filter, Infinite Impulse Response (IIR) filter and Fast Fourier Transform (FFT). The FIR filter core is based on the symmetrical realization form, the IIR filter core is based on the Second Order Sections (SOS) archit...

ADNAN SALEEM Implementation and Performance Analysis of Wishbone Shared Bus for Single Master-Multiple Slaves

ADNAN SALEEM: Implementation and Performance Analysis of Wishbone Shared Bus for Single Master-Multiple Slaves TAMPERE UNVIERSITY OF TECHNOLOGY Master of Science Thesis, 55 pages Month and year of completion: April 2015 Master’s Degree in Information Technology Major: Digital and Computer Electronics Examiner(s): Prof. Timo D. Hämäläinen, Erno Salminen